# Create a virtual clock (needed for timing analysis)

create_clock -period 40.000 -name virtual_clk

# Set delays based on analytical calculations
set_input_delay -clock virtual_clk -max 1.000 [get_ports A*]
set_input_delay -clock virtual_clk -max 1.000 [get_ports B*]
set_output_delay -clock virtual_clk -max 2.000 [get_ports P*]

# Set max delay for the critical path (longest delay)
set_max_delay -from [get_ports A*] -to [get_ports P*] 35.000




set_property IOSTANDARD LVCMOS33 [get_ports {A[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[6]}]
set_property PACKAGE_PIN R2 [get_ports {A[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {P[0]}]
set_property PACKAGE_PIN T1 [get_ports {A[6]}]
set_property PACKAGE_PIN U1 [get_ports {A[5]}]
set_property PACKAGE_PIN W2 [get_ports {A[4]}]
set_property PACKAGE_PIN R3 [get_ports {A[3]}]
set_property PACKAGE_PIN T2 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property PACKAGE_PIN V2 [get_ports {A[0]}]
set_property PACKAGE_PIN W13 [get_ports {B[7]}]
set_property PACKAGE_PIN W14 [get_ports {B[6]}]
set_property PACKAGE_PIN V15 [get_ports {B[5]}]
set_property PACKAGE_PIN W15 [get_ports {B[4]}]
set_property PACKAGE_PIN W16 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
set_property PACKAGE_PIN V16 [get_ports {B[1]}]
set_property PACKAGE_PIN V17 [get_ports {B[0]}]
set_property PACKAGE_PIN L1 [get_ports {P[15]}]
set_property PACKAGE_PIN P1 [get_ports {P[14]}]
set_property PACKAGE_PIN N3 [get_ports {P[13]}]
set_property PACKAGE_PIN P3 [get_ports {P[12]}]
set_property PACKAGE_PIN U3 [get_ports {P[11]}]
set_property PACKAGE_PIN W3 [get_ports {P[10]}]
set_property PACKAGE_PIN V3 [get_ports {P[9]}]
set_property PACKAGE_PIN V13 [get_ports {P[8]}]
set_property PACKAGE_PIN V14 [get_ports {P[7]}]
set_property PACKAGE_PIN U14 [get_ports {P[6]}]
set_property PACKAGE_PIN E19 [get_ports {P[1]}]
set_property PACKAGE_PIN U16 [get_ports {P[0]}]

set_operating_conditions -design_power_budget 2.0

set_property PACKAGE_PIN T3 [get_ports {A[1]}]
set_property PACKAGE_PIN W17 [get_ports {B[3]}]
set_property PACKAGE_PIN U15 [get_ports {P[5]}]
set_property PACKAGE_PIN W18 [get_ports {P[4]}]
set_property PACKAGE_PIN V19 [get_ports {P[3]}]
set_property PACKAGE_PIN U19 [get_ports {P[2]}]
